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HI2315
August 1997
10-Bit, 80 MSPS D/A Converter (Ultra-Low Glitch Version)
Description
The HI2315 is a 10-bit, 80MHz, high speed, low power CMOS D/A converter. The converter incorporates a 10-bit input data register with current outputs. The HI2315 includes a power down feature that reduces power consumption and a blanking control. The on-chip bandgap reference can be used to set the output current range of the D/A.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 80MHz * Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mW * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * TTL/CMOS Compatible Inputs * Built in Bandgap Voltage Reference * Power Down and Blanking Control Pins * Low Glitch * Pin Compatible with Sony CXD2306 * Direct Replacement for Sony CXD2315Q
Ordering Information
PART NUMBER HI2315JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S
Applications
* Wireless Communications * Direct Digital Frequency Synthesis * Signal Reconstruction * Test Equipment * High Resolution Imaging and Graphics Systems
Pinout
HI2315 (MQFP) TOP VIEW
D0 (LSB)
DVDD
DVSS
D3 D4 D5 D6 D7 D8 D9 (MSB) NC
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
AVSS
NC
NC
D2
D1
IO IO VG AVDD AVDD VREF SREF IREF
DVDD
DVSS
CE
NC
VB
CLK
BLK
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4119.1
10-1
HI2315 Functional Block Diagram
(LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DVDD BLK DVDD DVSS DVSS CLK VB CE 30 31 32 1 2 3 4 5 6 7 28 10 13 15 27 9 14 11 18 SREF CLOCK GENERATOR 21 AVDD BIAS VOLTAGE GENERATOR BAND GAP REFERENCE 20 AVDD CURRENT CELLS (FOR FULL SCALE) + DECODER 19 VREF DECODER LATCHES 6 MSBs CURRENT CELLS 4 LSBs CURRENT CELLS 24 IO 25 AVSS 23 IO
22 VG
-
17 IREF
Pin Descriptions
PIN NO. 30 to 32 1 to 7 SYMBOL D0 to D9
30 TO 7 DVSS
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital Input.
10
BLK
DVDD 10 DVSS
Blanking pin. No signal (0V output) at high and output state at low.
14
VB
DVDD
DVDD
Connect a capacitor of approximately 0.1F.
14
+
-
DVSS
9
CLK
DVDD
Clock pin.
9
DVSS
10-2
HI2315 Pin Descriptions
PIN NO. 15, 27 25 17 (Continued) EQUIVALENT CIRCUIT Digital GND. Analog GND.
AVDD AVDD
SYMBOL DVSS AVSS IREF VREF VG
DESCRIPTION
Connect resistance "16R" which is 16 times output resistance "R". Sets output full scale value.
19 22
AVDD
17
+
-
Connect a capacitor of approximately 0.1F.
19
AVSS
AVDD
AVSS
22
AVSS
20, 21 24
AVDD IO
AVDD
Analog VDD . Current Output pin. Output can be retrieved by connecting resistance. The standard is 200. Inverted Current Output pin. Connect to GND normally.
23
IO
24
AVSS AVDD 23
AVSS
13, 28 11
DVDD CE
DVDD
Digital VDD . Chip Enable pin. No signal (0V output) at high makes power consumption minimum.
11
DVSS
18
SREF
AVDD
18
Independent Constant-Voltage Source Output pin using band gap reference. Stable voltage independent of the fluctuation for supply voltage can be obtained by connecting to VREF . See Application Circuit 2 for details.
AVSS
10-3
HI2315
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (MQFP Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . .VSS -0.5V to VDD + 0.5V Output Voltage (IOUT). . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V 0.25V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0V 0.25V Reference Input Voltage (VREF). . . . . . . . . . . . . . . . . . .0.5V to 2.0V Clock Pulse Width (tPW1, tPW0) . . . . . . . . . . . . . . . . . . 6.25ns (Min) Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Maximum Conversion Rate Linearity Error Differential Linearity Error Output Full-Scale Voltage Output Full-Scale Current Output Off-Set Voltage Output Impedance Supply Current Digital Input Current
TA = 25oC, fCLK = 80MHz, VDD = 5V, R = 200, VREF = 2.0V, 16R = 3.3k SYMBOL n fMAX EL ED VFS IFS VOS TEST CONDITIONS MIN 80 -1.5 -0.5 1.8 9.0 IDD -5 2.45 1.8 3.0 3.0 5.0 ROUT = 200, 2VP-P TA = 25oC 1.0 TYP 10 1.94 9.7 300 1.94 5 1.2 MAX 1.5 0.5 2.0 10 1 30 5 0.85 2.0 30 1.0 1.0 1.4 UNITS Bit MHz LSB LSB V mA mV k mA A A V V V ns ns ns ns pV/s % Degrees V
High Level Low Level
IIH IIL VIH VIL VOC tS tH tr tPD GE DG DP SREF
Digital Input Voltage
High Level Low Level
Accuracy Guarantee Output Voltage Range Setup Time Hold Time Rise Time Propagation Delay Time Glitch Energy Differential Gain Differential Phase SREF Output Voltage
10-4
HI2315 Test Circuits
10-BIT COUNTER WITH LATCH 30 D0 (LSB) 31 0.1 7 9 D9 (MSB) VG 22 CLK 2V AVDD IO 23 200 OSCILLOSCOPE
10 BLK CLK 80MHz (MAX) SQUARE WAVE 11 CE 14 VB 0.1
VREF 19
5K AVSS
IREF 17 3.3K
FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT
30 D0 (LSB) CONTROLLER 31
IO 23 0.1 AVDD 200
DVM
7 9
D9 (MSB) VG 22 CLK 2V
10 BLK CLK 80MHz SQUARE WAVE 11 CE 14 VB 0.1
VREF 19
5K AVSS
IREF 17 3.3K
FIGURE 2. DC CHARACTERISTICS TEST CIRCUIT
30 D0 (LSB) 31
IO 23 0.1 AVDD 200
OSCILLOSCOPE
7 FREQUENCY DEMULTIPLIER 9
D9 (MSB) VG 22 CLK 2V
10 BLK CLK 10MHz (MAX) SQUARE WAVE 11 CE 14 VB 0.1
VREF 19
5K AVSS
IREF 17 3.3K
FIGURE 3. PROPAGATION DELAY TIME TEST CIRCUIT
10-BIT COUNTER WITH LATCH
30 D0 (LSB) 31
IO 23 0.1 AVDD 200 OSCILLOSCOPE
7 DELAY CONTROLLER CLK 1MHz SQUARE WAVE 9
D9 (MSB) VG 22 CLK 2V
10 BLK 11 CE
VREF 19
5K AVSS
DELAY CONTROLLER
14 VB 0.1
IREF 17 3.3K
FIGURE 4. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
10-5
HI2315 Timing Diagram
tPW1 CLK tS tH tS tH tS tH tPW0
TABLE 1. I/O CORRESPONDENCE TABLE (2.00V Output Full Scale Voltage) INPUT CODE MSB LSB 2.0V OUTPUT VOLTAGE
1111111111
DATA tPD
* * *
100%
1000000000 * * *
1.0V
D/A OUT tPD tPD
50% 0%
0000000000
0V
Typical Application Circuits
R3 R1 C C 24 23 22 21 20 19 18 17 R4 R2 AVDD DVDD
AVSS
DVSS
IO IO VG AVDD AVDD VREF SREF IREF 25 AVSS NC 16 26 NC 27 DVSS 28 DVDD C 29 NC 30 D0 31 D1 32 D2 D3 1 DVSS 15 VB 14 C DVDD 13 NC 12 CE 11 BLK 10 CLK 9 NC 8 CLOCK INPUT
D4 2
D5 3
D6 4
D7 5
D8 6
D9 7
NOTE: 2. When 5.0V supply voltage (DVDD and AVDD). Digital input from pins 30 to 32 and pins 1 to 7. Pin 18 is Left Open When Using Normally. R1 = 200, R2 = 3.3 (Resistance 16 Times R1), R3 = 3.0k, R4 = 2.0k, C = 0.1F. FIGURE 5. APPLICATION CIRCUIT 1
10-6
HI2315 Typical Application Circuits
(Continued)
AVDD R1 C C 24 23 22 21 20 19 18 17 R2
DVDD
AVSS
DVSS
IO IO VG AVDD AVDD VREF SREF IREF 25 AVSS NC 16 26 NC 27 DVSS 28 DVDD C 29 NC 30 D0 31 D1 32 D2 D3 1 DVSS 15 VB 14 C DVDD 13 NC 12 CE 11 BLK 10 CLK 9 NC 8 CLOCK INPUT
D4 2
D5 3
D6 4
D7 5
D8 6
D9 7
NOTE: 3. When 5.0V supply voltage (DVDD and AVDD). Digital input from pins 30 to 32 and pins 1 to 7. R1 = 200, R2 = 2.0k, C = 0.1F. FIGURE 6. APPLICATION CIRCUIT 2
Typical Performance Curves
OUTPUT FULL SCALE VOLTAGE (V) V = 0.2mV/oC 1.95
OUTPUT FULL SCALE VOLTAGE (V)
2.0
1.0
1.93
0 1.0 REFERENCE VOLTAGE (V) 2.0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC)
FIGURE 7. OUTPUT FULL SCALE VOLTAGE (VFS) vs REFERENCE VOLTAGE (VREF)
FIGURE 8. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
10-7
HI2315 Typical Performance Curves
V = 0.7mV/oC 1.25 SREF OUTPUT VOLTAGE (V)
(Continued)
CURRENT CONSUMPTION (mA) 0 25 50 75
30
1.15
20
0 -25 AMBIENT TEMPERATURE (oC)
0 1 10 20 30 40 OUTPUT FREQUENCY (MHz)
FIGURE 9. SREF vs AMBIENT TEMPERATURE NOTE:
FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION
4. Standard Measurement Conditions and Description: VDD = 5.0V, VREF = 2.0V, R = 200, 16R - 3.3k, TA = 25oC. The temperature characteristics of external input data in Figure 10 = all "0" and "1" of rectangular wave; clock frequency = 80MHz.
GE (Glitch Energy)
GE, as described in the HI2315, is a spike noise which appears synchronizing with the clock falling edge when the input data (for 1 to 1024 input) changes to 128, 256, 384, 512, 640, 768, 896, and 1024. Figure 11 shows the change state of GE for the staircase wave output, and Figure 12 shows the repetitive output waveform where the GE appears. These figures exhibit the difference of this IC from the convention device. The HI2315 reduces the GE as shown in Figures 11 and 12.
2.0 ANALOG OUTPUT (V) CONVENTIONAL DEVICE
1.0 HI2315
0
512 DIGITAL INPUT (V)
1024
CLK
FIGURE 11. CHANGE OF GE FOR STAIRCASE WAVE OUTPUT
10-8
HI2315
HI5780 (GE TYP = 200pV/S)
HI2315 (GE TYP = 10pV/S)
FIGURE 12. REPETITIVE OUTPUT WAVEFORM WHERE GE APPEARS (FOR 200, 2VP-P OUTPUT)
Notes On Operation
* Selecting the Output Resistance - HI2315 is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin. Specifications: Output full-scale voltage VFS (Max) = 2.0V Output full-scale current IFS (Max) = 10mA - Calculate the output resistance from VFS = IFS x R. Connect a resistance sixteen times the output resistance to the reference current pin IREF . In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following: VFS = VREF x 16 R/R'. - R is the resistor to be connected to the IO and R' is the resistor to be connected to the IREF . Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data settling time. Set the best values according to the purpose of use. * Correlation between Data and Clock - For the HI2315 to display the desired performance as a D/A converter, the data transmitted form outside and the clock must be synchronized properly. Adjust the setup time (tS) and hold time (tH) as specified in "Electrical Characteristics." * VDD , VSS - Separate the analog and digital signals around the device to reduce noise effects. By-pass the VDD pin to each GND with a 0.1F ceramics capacitor as near to the pin as possible for both the digital and analog signals. * Latch up - The AVDD and DVDD pins must be able to share the same power supply of the board. This is prevent latch up caused by potential difference between the two pins when the power is turned on. * IREF pin - The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. * VG Pin - It is recommended to use a 1F capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1F. * SREF - The SREF is independent regulated current source. By connecting it to the VREF , stable output amplitudes that do not depend on fluctuations in the power supply can be obtained. - In this case, as VFS = SREF x 16R/R', set the VFS according to R'. - Do not use this pin as a reference power supply for other ICs because this is dedicated for the D/A converter.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
10-9

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